1. Field of the Invention
The present invention relates to a method of forming a structured metallization on a semiconductor wafer and especially to methods which are suitable for producing a rewired area on a chip surface.
2. Description of Prior Art
The increasing degree of miniaturization of electronic systems necessitates that the chip housings become smaller and smaller. An optimum utilization of the printed circuit board surface can only be achieved by the use of flip-chip mounting for unhoused chips.
The pad arrangement and the pitch of presently available chips are limited by the possibilities of wire bonding technology, since, in the foreseeable future, most of the chips will be used in a housed form. Hence, a very small pitch and also very small pad areas are used for high-pole chips. Pad sizes of 80.times.80 Im and a pitch of 100 Im are normally used. In the case of configurations which are so small, contacting by bonding wires can be realized, but the classic flip-chip technique cannot be used for this purpose.
When the above-mentioned fine pitch is used, a large number of problems arises with regard to the classic flip-chip technique. These problems concern solder bridges between neighbouring solder bumps, solder-stop lacquer openings on the printed circuit board as well as the equipment for the ultrafine distances (pitch).
In order to avoid the above-mentioned problems, chip housings are known in the field of technology in the case of which the connections of the chip are rearranged in such a way that a planar configuration is obtained. An example of such a planar arrangement is shown in FIG. 1 where a plurality of marginal pads, reference numeral 10, are rewired thus forming a corresponding plurality of pads in a planar arrangement, reference numeral 12. A further example of rewiring is e.g. the rewiring of two pads on a chip to form very large bumps, which are arranged on a chip surface, such very large bumps being referred to as megabumps in the field of technology.
There are various possibilities of realizing a rewiring technique on the chip surface for changing the bump geometry and the connections, and a distribution of the connections from the edge of the chip such that a planar distribution is obtained. According to the prior art, metallization layers are electrodeposited, the metallization layers being then structured by photolithography, whereupon the metallization areas which are not required are etched. The full-area deposition of metal can be carried out not only by electro-deposition but also by vapour deposition.
According to the conventional rewiring method, the following sequence of process steps takes place. Initially, a photo-structurable dielectric is applied to a main surface of a semiconductor wafer with a passivation layer for defining bond pads. Subsequently, the bond pads in the dielectric are opened. Following this, a sputtering process is carried out for producing a full-area metallization on the wafer, i.e. on the bond pads and on the dielectric. The full-area metallization is then structured making use of a photoresist mask, whereby the rewiring metallization is defined. An electrodeposition of metal is then carried out on the thus defined thin metallization. Following this, the residual photoresist mask is removed and the base metallization is subjected to selective etching. Finally, a solder resist mask, which defines the planar pads, is applied to the surface of the wafer.
Primarily the costs for the sputtering equipment, which are normally very high, represent a disadvantage of the known method. Furthermore, when the full-area metallization has been produced on the wafer, a further photolithographic method must be carried out making use of a photoresist mask. The known method is therefore comparatively complicated.
EP-A-0151413 refers to methods of selective currentless metal deposition on dielectric surfaces. In the case of these methods a dielectric surface is treated by activating preselected areas of the surface by means of a pretreatment solution, e.g. a palladium-chloride solution, whereupon a currentless metal deposition is carried out on the activated areas.
J. Electrochem. Soc. 1989, Vol. 136, No.2, pp. 456-462, disclose methods of selective currentless metal deposition, which are used in the production of integrated circuits and especially for producing multilevel interconnections in VLSI circuits. These methods comprise the step of forming conductor patterns by depositing first a thin aluminium layer on an SiO.sub.2 surface so as to form an adhesive layer between the future metallization and the SiO.sub.2 layer. Following this, a currentless metal deposition is carried out, e.g. by means of a suitable mask, for producing the desired conductor patterns.
IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B, 1995, Vol. 18, No. 2, pp. 334-338, described methods for currentless nickel/copper deposition on bond pads of a silicon wafer provided with a passivation layer, the nickel/copper being deposited for producing metal bumps.
JP-A-206680 discloses the formation of a layer of an activated dielectric material on a substrate for performing then a currentless deposition of metal layers on lateral surfaces of the activated dielectric material. In order to prevent a deposition on the surface of the activated dielectric material extending parallel to the substrate, a layer of inactive dielectric material is applied to this surface.